Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A three dimensional (3D) package may contain two or more integrated circuits (ICs) stacked vertically so that they occupy less space and/or have greater connectivity. In some implementations, a carrier substrate containing through silicon vias (TSVs) may be used to connect multiple ICs together in a package. In some 3D packages, the stacked ICs may be wired together along their edges slightly increasing the dimensions of the package and typically including an extra interposer layer between the ICs. The TSVs may replace edge wiring by creating vertical connections through the body of the ICs eliminating the added length or width due to edge wiring and the additional thickness (and fabrication steps) associated with the interposer layer. However, TSVs may complicate the fabrication process.
In addition, stacked ICs may be prone to heat related performance issues more so than individual ICs because heat accumulation due to multiple ICs operating in close proximity (attached to each other) may affect each of the ICs. Various approaches to enhance heat dissipation in stacked ICs may add yet more complexities to the fabrication process.